EDGE AI POD

What if the only way to get real gains at the edge is to redesign everything—from the silicon atoms to the app you deploy? That’s the bet Professor-Founder Mohammed Ali made with EMAS, and the results are striking: continuous inference at milliwatts, microsecond wake/sleep cycles, and real benchmarks that hold up against the best in class while burning a fraction of the energy.

We walk through how a RISC-V core, dual AI accelerators, and an MRAM/RRAM-backed memory system work together to keep weights on-chip, slash data movement, and power-gate aggressively without losing state. The compiler handles pruning, quantization, and on-the-fly compression to achieve around 1.3 bits per weight without torpedoing accuracy, while a custom memory controller mitigates non-volatile quirks like endurance and read variability. Instead of chasing TOPS, the stack optimizes bandwidth, dataflow, and timing to match the realities of sensors and batteries.

The story gets especially interesting with drones. Since propellers—not processors—dominate energy use, EMAS applies tiny AI to the control problem, redistributing load across rotors in real time and extending flight endurance by 60% or more in hardware-in-the-loop simulations. We also dig into wearables and time-series workloads like ECG, audio, and vibration, where sparse sampling pairs perfectly with microsecond power gating. If you build at the edge, the dev experience matters: you’ll hear about the virtual dev kit with remote access to real silicon, a compact evaluation board with modular sensors, and an SDK that plugs into TensorFlow, PyTorch, and Zephyr. Advanced users can map trained models via a CLI; newcomers can lean on a NAS-based flow that proposes architectures meeting strict memory and power budgets.

If you care about edge AI, battery life, and shipping reliable products, this conversation is a blueprint for co-designing across the stack to unlock 10–200x energy gains without giving up performance. Subscribe, share with a teammate who owns your edge roadmap, and leave a review with the one use case you’d optimize first.
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What if your model pipeline started with a simple goal—your dataset, your target chip, and your latency or energy budget—and ended with measured results on real hardware? We sit down with Model Cat CEO Evan Petritis to explore how AI can build on-device AI through a closed loop that’s grounded in silicon, not estimates or hopeful benchmarks. From a live demo to a tour of their “chip farm,” we dig into how the platform searches architectures, tunes hyperparameters, and validates performance using vendor kernels and compilers across MCUs, MPUs, and specialized accelerators.

We share the story behind the rebrand from Eta Compute to Model Cat and why the shift matters: AI research moves too fast for traditional, component-by-component toolchains. Evan breaks down five pillars for trustworthy, autonomous model creation—closed-loop goals, reality grounding, system-level intent, modular learning from new research, and a single-step, transparent experience. You’ll hear how teams can upload datasets, get automated analytics on splits and distribution shifts, set constraints like sub–5 ms inference or energy per inference, and see success predictions before training even starts.

The demo highlights the silicon library and how each device is profiled in depth—supported ops, kernel speeds, memory footprints—so accuracy, latency, and energy are measured on the actual target. Results come as clear Pareto trade-offs with downloadable artifacts that reproduce on-device. We also field audience questions on exporting to Keras and TFLite, supporting time-series and audio keyword spotting, integrating labeling partners, onboarding new MCUs and accelerators, and the roadmap toward neuromorphic targets and cost estimation.

If you care about edge AI, embedded ML, and shipping models that meet real-world constraints, this conversation shows a practical path forward: use AI to navigate the fire hose of research, then prove it on silicon. Enjoy the episode—and if it sparks ideas, subscribe, leave a review, and share it with a teammate who lives in notebooks but dreams in devices.
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We share new data showing why drivers see generative AI as a defining force in mobility and how edge inference makes cars faster, safer, and more personal. We map the use cases, hardware shifts, and the move to software-first procurement with clear guidance for builders.

• survey highlights on generative AI as a mobility megatrend
• definitions and examples of circular economy in vehicles
• priority edge use cases in ADAS, safety, and infotainment
• hidden value in predictive maintenance and intrusion detection
• why inference runs on the edge for latency and reliability
• constraints around cost, memory, and over-the-air updates
• NPU rise over GPU and evolving CPU roles
• software-first buying and model portability trade-offs
• smarter sensors, radar AI, and neuromorphic paths
• hybrid architectures for sensor fusion and efficiency

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Tired of choosing between performance and freedom? We sit down with Stefan Crossin, CEO and co‑founder of YASP, to unpack how a hardware‑aware AI compiler can speed up training, simplify deployment, and finally make model portability real. The story starts with a distributed team in Freiburg and Montreal and moves straight into the heart of the problem: most AI groups burn time on infrastructure and juggle separate stacks for training and inference, all while staying tethered to one dominant vendor’s software ecosystem.

Stefan lays out a different path. YASP converts models into a clean intermediate representation, plugs into the tools teams already use, and applies a closed‑loop optimization system that learns the target hardware. Instead of forcing a new language or workflow, a few lines of integration unlock dynamic kernel generation, graph‑level tuning, and one‑click deployment to different chips, clouds, or edge devices. The result is a practical bridge between “write once” ideals and real‑world performance, where being hardware‑aware—not hardware‑bound—delivers speed without lock‑in.

We also dive into the market dynamics behind portability. Incumbents protect moats; challengers need bridges. Cloud providers fear shorter runtimes but win when customers get more value per dollar and per watt. With credible benchmarks showing meaningful gains in training and inference, YASP is courting chip makers, CSPs, and end users through a focused beta, a clear roadmap to launch, and a business model that combines free access with subscription tiers. If you’ve been waiting for proof that AI can be both faster and freer across architectures, this conversation makes the case with clarity and detail.

Enjoy the episode? Follow the show, share it with a colleague, and leave a quick review—what platform or accelerator would you target first with true portability?
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What if the smartest part of AI isn’t in the cloud at all—but right next to the sensor where data is born? We pull back the curtain on the rapid rise of edge AI and explain why speed, privacy, and resilience are pushing intelligence onto devices themselves. From self‑driving safety and zero‑lag user experiences to battery‑friendly wearables, we map the forces reshaping how AI is built, deployed, and trusted.

We start with the hard constraints: latency that breaks real‑time systems, the explosion of data at the edge, and the ethical costs of giant data centers—energy, water, and noise. Then we dive into the hardware leap that makes on‑device inference possible: neural processing units delivering 10–100x efficiency per watt. You’ll hear how a hybrid model emerges, where the cloud handles heavy training and oversight while tiny, optimized models make instant decisions on sensors, cameras, and controllers. Using our BLERP framework—bandwidth, latency, economics, reliability, privacy—we give a clear rubric for deciding when edge AI wins.

From there, we walk through the full edge workflow: on‑device pre‑processing and redaction, cloud training with MLOps, aggressive model optimization via quantization and pruning, and robust field inference with confidence thresholds and human‑in‑the‑loop fallbacks. We spotlight the technologies driving the next wave: small language models enabling generative capability on constrained chips, agentic edge systems that act autonomously in warehouses and factories, and neuromorphic, event‑driven designs ideal for always‑on sensing. We also unpack orchestration at scale with Kubernetes variants and the compilers that unlock cross‑chip portability.

Across manufacturing, mobility, retail, agriculture, and the public sector, we connect real use cases to BLERP, showing how organizations cut bandwidth, reduce costs, protect privacy, and operate reliably offline. With 2026 flagged as a major inflection point for mainstream edge‑enabled devices and billions of chipsets on the horizon, the opportunity is massive—and so are the security stakes. Join us to understand where AI will live next, how it will run, and what it will take to secure a planet of intelligent endpoints. If this deep dive sparked ideas, subscribe, share with a colleague, and leave a review to help others find the show.
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